1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile memory, for example, a semiconductor non-volatile memory device such as a flash EEPROM, and to a decoder circuit thereof.
2. Description of the Related Art
In recent years, flash memories have been the subject of vigorous development. The mainstream of development has been the hot electron/Fowler-Nordheim (FN) tunnel injection phenomenon wherein channel hot electrons are injected into a floating gate at the time of writing and the electrons are discharged from the floating gate to a source at the time of erasing by the FN tunneling.
More specifically, at the time of writing, 12V is applied to a control gate, 5 to 7V is applied to a drain, 0V is applied to a source and a substrate, and the hot electrons generated in the channel are injected into the floating gate, whereby data is written.
At the time of erasing, 0V or a negative voltage of from xe2x88x929 to xe2x88x9212V is applied to the control gate, a positive voltage of 12V or 5V is applied to the source, 0V is applied to the substrate, and the drain is kept at the floating state, to thereby discharge the electrons from the floating gate to source by the FN tunneling, whereby data is erased.
However, this hot electron/FN tunnel injection method has a problem in that it is difficult to lower the voltage, the channel current required for the writing is large and therefore the booster circuit becomes big, etc.
In a NOR type flash memory, the lowering of voltage is the biggest issue.
In the past, there has been proposed a NOR type flash memory which solves these problems, has the feature of enabling NOR type random access, and, further, incorporates the merits of NAND type performance, i.e., a high writing speed (refer to, for example, NIKKEI MICRODEVICES pp. 66-67, October 1992).
FIG. 1 is a view of the arrangement and configuration of a so-called NOR type flash memory proposed in the past.
In FIG. 1, MILa denotes a main bit line; SBLa denotes a sub-bit line; SRLa denotes a source line, STa a selection transistor serving as a selection gate; SGLa, a selection gate line, MTa0 to MTa3 denote memory transistors; and WLa0 to WLa3 denote word lines; respectively.
In this memory cell, as shown in FIG. 1, the sub-bit lines SBL are branched from the main bit line MILa, and a plurality of memory transistors (four in this example) are arranged in parallel at each branched sub-bit line SBL via the selection transistors ST.
FIGS. 2A and 2B are views of an example of an actual construction of the flash memory of FIG. 1, in which FIG. 2A is a plan view of the principal part of the memory cell of FIG. 1; and FIG. 2B is a cross-sectional view taken along a line Axe2x80x94A in FIG. 2A.
In the present construction, a third layer of polycrystalline silicon (3-POLY) is used for the sub-bit lines SBL, and a first layer of aluminum (1-Al) is used for the main bit lines MIL (refer to the above-described document).
In this way, in the above-mentioned flash memory, 3-POLY is used as the material of the sub-bit lines SBL, and therefore the resistance thereof becomes about 200 times as large as that of aluminum.
Accordingly, the conventional flash memory is effective when thinking only of the cell size, but where the improvement of the accessing time etc. are taken into account, desirably aluminum with its low resistivity is used for the sub-bit lines SBL.
When adopting such a construction, to suppress the delay of the word lines WL, it becomes indispensable to use 1-Al for the sub-bit lines SBL and to use a second layer of aluminum (2-Al) for the main bit lines.
However, in the conventional memory arrangement of FIGS. 2A and 2B mentioned above, the arrangement of the memory cells is determined by the 2-Al having the widest line width and line pitch, and there is a problem in that the memory cells cannot be arranged on the chip with high efficiency.
Describing this problem in further detail, the pitch of the word lines WL of the flash memory is small, and therefore it is impossible to lay the word lines in a one-to-one correspondence(relationship) at the 2-Al. Accordingly, the only system which can be used is that of a main row decoder and sub-row decoder.
For this reason, in the case of a memory cell having the construction of FIGS. 2A and 2B, the number of masks and number of manufacturing steps in the production process are increased in comparison with the system using 1-Al.
Also, in the construction of FIG. 2, when assuming 1-Al is used for the sub-bit lines and 2-Al is used for the main bit lines, the step difference of the contact of 2-Al and the diffusion layer becomes very large, and it is extremely difficult to arrange direct contact between the 2-Al and the diffusion layer, so a technique of for example burying with tungsten becomes necessary.
Also, it is clear that neither of the layers 1-Al and 2-Al can be formed in the word line direction. When it is intended to form the layer 1-Al in the word line direction, the size in the vertical direction must be slightly sacrificed.
Further, when assuming that the main bit lines are formed at 2-Al, generally the pitch at the 2-Al becomes larger than the pitch of the 1-Al even if use is made of the technique of burying with tungsten, and therefore there is a large possibility of inducing an increase of the size of the cell in the lateral direction.
From the above, in the construction of FIG. 1 and FIGS. 2A and 2B, it is not possible to replace the 3-POLY by 1-Al and the 1-Al by 2-Al, an improvement of the accessing time cannot be achieved, and also the production process cannot be simplified.
Moreover, also a method of using the diffusion layer for the sub-bit lines has been proposed, but the resistance of the diffusion layer is about 2000 times as large as that of aluminum, and thus it is not suitable for the enhancement of speed.
Also, in this method, there are many problems such as realization of a quality of an oxide film on the diffusion layer into which an impurity is added at a high density, a short channel length, a large coupling ratio (ratio of control gate-floating gate capacitance with respect to the whole), etc., and thus this is not yet practical.
An object of the present invention is to provide a semiconductor non-volatile memory device operable by low voltage.
Another object of the present invention is to provide a semiconductor non-volatile memory device which can be improved in operation speed such as accessing time.
Still another object the present invention is to provide a semiconductor non-volatile memory device which can be produced by a simplified process.
Yet another object the present invention to provide a semiconductor non-volatile memory device which can be produced at a low cost.
Still another object the present invention is to provide a semiconductor non-volatile memory device which can prevent a malfunction, such as a non-intended write operation.
Another object of the present invention is to provide a decoder circuit which can be improved in operation speed.
According to the present invention, there is provided a semiconductor non-volatile memory device including one or more memory blocks, each memory block comprising:
a main bit line,
a plurality of sub-bit lines connected to memory transistors and arranged in parallel with respect to the main bit line, and
two cascade-connected selection gates provided between the main bit line and sub-bit lines respectively and selectively connecting one of the sub-bit lines to the main bit line.
Further, according to the present invention, there is provided a semiconductor non-volatile memory device including one or more memory blocks, each memory block comprising:
a main bit line,
a plurality of sub-bit lines connected to memory transistors and arranged in parallel with respect to the main bit line, and
selection gates provided between the main bit line and sub-bit lines respectively and selectively connecting one of the sub-bit lines to the main bit line,
a selection gate for sub-bit lines and another selection gate for sub-bit lines being arranged on opposite sides across the memory cell arranged area.
Preferably, there is provided a circuit for holding the non-selected sub-bit lines at a reference potential.
More preferably, one of the above-described two selection gates comprises a depletion type transistor.
Further, according to the present invention, there is provided a semiconductor non-volatile memory device having a plurality of memory transistors with drains connected to the bit lines, sources connected to a common source line, and control gates connected to the word lines, wherein selection gates are provided at the source side of each memory transistor, and
wherein, at the time of writing, a predetermined voltage is applied to the control gate of non-selected memory transistor(s) and the selection gate is held at the predetermined potential to cut the current path of the channel of the transistor(s).
Preferably, the selection gate is formed by side walls.
More preferably, at the time of writing, the writing pulses to the bit lines are sequentially applied at predetermined intervals.
More preferably, a plurality of bit lines are divided into a plurality of groups.
Further, according to the present invention, there is provided a decoder circuit which performs the reading of data from a memory cell selected by a word line, the writing of data into the memory cell, and the erasing of data, comprising:
a plurality of sub-decoder used for reading and connected to the word line and
a sub-decoder used only for writing and erasing commonly provided for the decoder circuit.